H8SX1663 datasheet(196/1158 Pages) RENESAS

196 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 144 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

CSXH7

CSXH6

CSXH5

CSXH4

CSXH3

CSXH2

CSXH1

CSXH0

R/W

CS and Address Signal Assertion Period Control 1

These bits specify whether or not the Th cycle is to be

inserted (see figure 6.3). When an area for which bit

CSXHn is set to 1 is accessed, one Th cycle, in which

the

CSn and address signals are asserted, is inserted

before the normal access cycle.

0: In access to area n, the

CSn and address assertion

period (Th) is not extended

1: In access to area n, the

CSn and address assertion

period (Th) is extended

(n = 7 to 0)

CSXT7

CSXT6

CSXT5

CSXT4

CSXT3

CSXT2

CSXT1

CSXT0

R/W

CS and Address Signal Assertion Period Control 2

These bits specify whether or not the Tt cycle is to be

inserted (see figure 6.3). When an area for which bit

CSXTn is set to 1 is accessed, one Tt cycle, in which

the

CSn and address signals are retained, is inserted

after the normal access cycle.

0: In access to area n, the

CSn and address assertion

period (Tt) is not extended

1: In access to area n, the

CSn and address assertion

period (Tt) is extended

(n = 7 to 0)

Note:

In burst ROM interface, the CSXTn settings are ignored during CPU read accesses.

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