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SH7124 Datasheet(PDF) 23 Page - Renesas Technology Corp |
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SH7124 Datasheet(HTML) 23 Page - Renesas Technology Corp |
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23 / 774 page  Section 1 Overview Rev. 4.00 Jul. 25, 2008 Page 3 of 750 REJ09B0243-0400 Items Specification Interrupt controller (INTC) • External interrupt pins SH7125: Five pins (NMI and IRQ3 to IRQ0) SH7124: Four pins (NMI and IRQ3 to IRQ1) • On-chip peripheral interrupts: Priority level set for each module • Vector addresses: A vector address for each interrupt source User debugging interface (H-UDI) • E10A emulator support Clock pulse generator (CPG) • Clock mode: Input clock can be selected from external input or crystal resonator • Four types of clocks generated: CPU clock: Maximum 50 MHz Bus clock: Maximum 40 MHz Peripheral clock: Maximum 40 MHz MTU2 clock: Maximum 40 MHz Watchdog timer (WDT) • On-chip one-channel watchdog timer • Interrupt generation is supported. |
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