SH7124 datasheet(32/774 Pages) RENESAS

32 / 774 page

Section 1 Overview

Rev. 4.00 Jul. 25, 2008 Page 12 of 750

REJ09B0243-0400

Classification

Symbol

I/O

Name

Function

RES

Power-on reset

When low, this LSI enters the power-

on reset state.

MRES

Manual reset

When low, this LSI enters the

manual reset state.

System control

WDTOVF

Watchdog timer

overflow

Output signal for the watchdog timer

overflow

If this pin needs to be pulled down,

use the resistor larger than

1 M

Ω to pull this pin down.

NMI

Non-maskable

interrupt

Non-maskable interrupt request pin

Fix to high or low level when not in

use.

Interrupts

IRQ3 to IRQ0

(SH7125)

IRQ3 to IRQ1

(SH7124)

Interrupt requests

3 to 0

Maskable interrupt request pins

Selectable as level input or edge

input. The rising edge, falling edge,

and both edges are selectable as

edges.

IRQOUT

Interrupt request

output

Shows that an interrupt cause has

occurred. The interrupt cause can be

recognized even in the bus release

state.

TCLKA,

TCLKB,

TCLKC,

TCLKD

MTU2 timer clock

input

External clock input pins for the timer

TIOC0A,

TIOC0B,

TIOC0C,

TIOC0D

I/O

MTU2 input

capture/output

compare

(channel 0)

The TGRA_0 to TGRD_0 input

capture input/output compare

output/PWM output pins

TIOC1A,

TIOC1B

(only in

SH7125)

I/O

MTU2 input

capture/output

compare

(channel 1)

The TGRA_1 to TGRB_1 input

capture input/output compare

output/PWM output pins

Multi function timer-

pulse unit 2 (MTU2)

TIOC2A,

TIOC2B

(only in

SH7125)

I/O

MTU2 input

capture/output

compare

(channel 2)

The TGRA_2 to TGRB_2 input

capture input/output compare

output/PWM output pins

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