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HD6433636SW Datasheet(PDF) 358 Page - Renesas Technology Corp |
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HD6433636SW Datasheet(HTML) 358 Page - Renesas Technology Corp |
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358 / 418 page ![]() 344 SCSR1—Serial control/status register 1 H'A1 SCI1 Bit Initial value Read/Write 7 — 1 — 6 SOL 0 R/W 5 ORER 0 R/(W) 4 — 1 — 3 — 1 — 0 STF 0 R/W 2 — 1 — 1 — 0 R Extended data bit Overrun error flag 0 Read Write * Start flag 0 Indicates that transfer is stopped Invalid 1 Read Write Read Write Indicates transfer in progress Starts a transfer operation 1 Read Write SO1 pin output level is low SO1 pin output level changes to low SO1 pin output level is high SO1 pin output level changes to high Note: Only a write of 0 for flag clearing is possible. * 0 [Clearing condition] After reading 1, cleared by writing 0 1 [Setting condition] Set if a clock pulse is input after transfer is complete, when an external clock is used SDRU—Serial data register U H'A2 SCI1 Bit Initial value Read/Write 7 SDRU7 Undefined R/W 6 SDRU6 Undefined R/W 5 SDRU5 Undefined R/W 4 SDRU4 Undefined R/W 3 SDRU3 Undefined R/W 0 SDRU0 Undefined R/W 2 SDRU2 Undefined R/W 1 SDRU1 Undefined R/W Stores transmit and receive data 8-bit transfer mode: 16-bit transfer mode: Not used Upper 8 bits of data |
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