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HD6433636SW Datasheet(PDF) 362 Page - Renesas Technology Corp |
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HD6433636SW Datasheet(HTML) 362 Page - Renesas Technology Corp |
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362 / 418 page  348 SCR3—Serial control register 3 H'AA SCI3 Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 0 CKE0 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W Clock enable CKE1 Bit 1 CKE0 Bit 0 Description Transmit end interrupt enable 0 Transmit end interrupt (TEI) disabled Communication Mode Clock Source SCK Pin Function 3 1 Transmit end interrupt (TEI) enabled Multiprocessor interrupt enable 0 Multiprocessor interrupt request disabled (ordinary receive operation) 1 Multiprocessor interrupt request enabled Until a multiprocessor bit value of 1 is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are disabled, and serial status register (SSR) flags RDRF, FER, and OER are not set. 0 0 Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output 1 Asynchronous Internal clock Clock output Synchronous Reserved 1 0 Asynchronous External clock Clock output Synchronous External clock Serial clock input 1 Asynchronous Reserved Synchronous Reserved [Clearing condition] Multiprocessor bit receives a data value of 1 Transmit enable 0 Transmit operation disabled (TXD is the transmit data pin) 1 Transmit operation enabled (TXD is the transmit data pin) Receive enable 0 Receive operation disabled (RXD is a general I/O port) 1 Receive operation enabled (RXD is the receive data pin) Receive interrupt enable 0 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled 1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled Transmit interrupt enable 0 Transmit data empty interrupt request (TXI) disabled 1 Transmit data empty interrupt request (TXI) enabled Reserved Reserved Reserved |
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