HD6433636SW datasheet(275/418 Pages) RENESAS

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Simultaneous Transmit/Receive: Figure 10.18 shows a typical flow chart for transmitting and

receiving simultaneously. After SCI3 synchronization, follow the procedure below.

Start

Read bit TDRE in SSR

Read RDRF in SSR

RDRF = 1?

Read received data in RDR

Read bit OER in SSR

OER = 1?

Continue

transmitting and

receiving?

Clear bits TE and

RE in SCR3 to 0

End

Read the serial status register (SSR),

and after confirming that bit TDRE = 1,

write transmit data in the transmit data

TDR, TDRE is automatically cleared to 0.

Read the serial status register (SSR),

and after confirming that bit RDRF = 1,

read the received data from the receive

data register (RDR). When data is read

from RDR, RDRF is automatically cleared

to 0.

To continue transmitting and receiving

serial data, read bit RDRF and finish

reading RDR before the MSB (bit 7) of the

present frame is received. Also read bit

When an overrun error occurs, read bit

OER in SSR. After the necessary error

processing, be sure to clear OER to 0.

Data transmission and reception cannot

take place while bit OER is set to 1. See

figure 10.16 for overrun error processing.

Note: When switching from transmit or receive

operation to simultaneous transmit/

receive operations, first clear the TE

bit and RE bit to 0, then set both these

bits to 1 simultaneously.

TDRE = 1?

Yes

Write transmit data in TDR

Overrun error processing

TDRE, check that it is set to 1, and write

the next data in TDR before the MSB (bit 7)

of the current frame has been transmitted.

When data is written to TDR, TDRE is

automatically cleared to 0; and when data

is read from RDR, RDRF is automatically

cleared to 0.

Figure 10.18 Simultaneous Transmit/Receive Flow Chart in Synchronous Mode

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