HD6433636SW datasheet(272/418 Pages) RENESAS

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SCI3 operates as follows during data transmission in synchronous mode.

SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data

written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).

Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is

requested.

If clock output is selected, SCI3 outputs eight serial clock pulses. If an external clock is used, data

is output in synchronization with the clock input.

Serial data is transmitted from pin TXD in order from LSB (bit 0) to MSB (bit 7).

After that, it checks TDRE at the same timing which it transmits the MSB (bit 7). If TDRE is 0,

data is transferred from TDR to TSR, and after the MSB (bit 7) is sent, transmission of the next

frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the MSB (bit 7) is sent, the

MSB state is maintained. A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1.

After data transmission ends, pin SCK

3 is held at the high level.

Note:

Data transmission cannot take place while any of the receive error flags (OER, FER, PER)

is set to 1. Be sure to confirm that these error flags are cleared to 0 before starting

transmission.

Figure 10.15 shows a typical SCI3 transmit operation in synchronous mode.

Serial

clock

Serial data

TDRE

TEND

Bit 0

Bit 7

Bit 0

Bit 1

Bit 6

Bit 7

Bit 1

TXI

request

TDRE cleared to 0

TXI

request

TEI request

1 frame

SCI3

operation

User

processing

Write data in TDR

Figure 10.15 Typical SCI3 Transmit Operation in Synchronous Mode

HD6433636SW Datasheet(PDF) 272 Page - Renesas Technology Corp

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