HD6433636SW datasheet(270/418 Pages) RENESAS

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Note:

When modifying the operation mode, transfer format or other settings, always be sure to

clear bits TE and RE first. When TE is cleared to 0, bit TDRE will be set to 1. Clearing

RE does not clear the status flags RDRF, PER, FER, or OER, or alter the contents of the

receive data register (RDR).

When an external clock is used in synchronous mode, do not supply the clock during

initialization.

Figure 10.13 shows a typical flow chart for SCI3 initialization.

Start

Clear TE and RE to 0 in SCR3

Select communication format in SMR

Set BRR value

Has a 1-bit

interval elapsed?

Set bits RIE, TIE, TEIE, and MPIE

in SCR3, and set TE or RE to 1

Set the transmit/receive format in the serial

mode register (SMR).

Write the value corresponding to the desired

bit rate to the bit rate register (BRR). Note that

this setting is not required when using an

external clock.

Wait for at least a 1-bit interval, then set

bits RIE, TIE, TEIE, and MPIE, and set bit

TE or RE in SCR3 to 1. Setting TE or RE

Note:

In simultaneous transmit/receive operations, the TE and RE bits should both be cleared to 0

or set to 1 simultaneously.

Yes

Wait

End

enables SCI3 to use the TXD or RXD pin.

The initial states in asynchronous mode

are the mark transmit state and the idle

receive state (waiting for a start bit).

Set bits CKE1 and CKE0

Select the clock using serial control

unused bits.

When the clock output is selected in the

asynchronous mode, a clock signal is

output immediately after setting bits CKE1

and CKE0 appropriately. When the clock

output is selected in the synchronous

mode, a clock signal is output immediately

after setting bits CKE1 and CKE0

appropriately and setting bit RE to 1.

Figure 10.13 Typical Flow Chart when SCI3 Is Initialized

HD6433636SW Datasheet(PDF) 270 Page - Renesas Technology Corp

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