HD6433636SW datasheet(293/418 Pages) RENESAS

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279

11.2.2

DTMF Load Register (DTLR)

Bit

76543210

—

DTL4

DTL3

DTL2

DTL1

DTL0

Initial value

11100000

Read/Write

—

R/W

DTLR is an 8-bit read/write register that specifies the ratio by which the clock frequency at the

OSC pins is divided for input to the DTMF generator.

Upon reset, DTLR is initialized to H'E0.

Bits 7 to 5—Reserved Bits: Bits 7 to 5 are reserved: they are always read as 1, and cannot be

modified.

Bits 4 to 0—OSC Clock Division Ratio 4 to 0 (DTL4 to DTL0): Bits 4 to 0 specify a division

ratio of the OSC clock frequency which will generate a 400-kHz clock for input to the DTMF

generator. The ratio is set as a counter value from 3 to 25, corresponding to OSC clock frequencies

of 1.2 to 10 MHz (in 400-kHz steps).

Description

Bit 4:

DTL4

Bit 3:

DTL3

Bit 2:

DTL2

Bit 1:

DTL1

Bit 0:

DTL0

Division Ratio

OSC Clock

Frequency

00000

Illegal setting

(initial value)

Illegal setting

1.2 MHz

1004

1.6 MHz

::::::

1100125

10 MHz

Illegal setting

Note: * Don’t care

These bits must be set to the correct value. Normal DTMF signal output frequencies will not be

obtained if these bits are set to a value not matching the clock input at the OSC pins. Operation is

not guaranteed if these bits are set to a value other than 3 to 25.

HD6433636SW Datasheet(PDF) 293 Page - Renesas Technology Corp

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