SH7052 datasheet(848/919 Pages) RENESAS

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24.3.2

Clock Timing

Table 24.7 shows the clock timing.

Table 24.7

Clock Timing

Conditions: V

CC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,

CC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC,

SS = PLLVSS = AVSS = 0 V, Ta = –40°C to 85°C.

When PV

CC1 = 3.3 V ±0.3 V, VCC = PVCC1.

When writing or erasing flash EEPROM, T

a = –40°C to 85°C.

Item

Symbol

Min

Max

Unit

Figures

Operating frequency

MHz

Figure 24.2

Clock cycle time

cyc

Clock low-level pulse width

—

Clock high-level pulse width

—

Clock rise time

—

8ns

Clock fall time

—

8ns

EXTAL clock input frequency

MHz

Figure 24.3

EXTAL clock input cycle time

cyc

100

200

EXTAL clock input low-level pulse width

EXL

—

EXTAL clock input high-level pulse width

EXH

—

EXTAL clock input rise time

EXR

—

8ns

EXTAL clock input fall time

EXF

—

8ns

Reset oscillation settling time

osc1

—

Figure 24.4

Standby return clock settling time

osc2

—

[Operating precautions]

The EXTAL, XTAL, and CK pins constitute a circuit requiring a power supply voltage of V

CC =

3.3 V

±0.3 V. Comply with the input and output voltages specified in the DC characteristics.

SH7052 Datasheet(PDF) 848 Page - Renesas Technology Corp

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