SH7052 datasheet(144/919 Pages) RENESAS

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Table 8.2

Name

Abbr.

R/W

Initial Value Address

Access Size

Bus control register 1

BCR1

R/W

H'000F

H'FFFFEC20 8, 16, 32

Bus control register 2

BCR2

R/W

H'FFFF

H'FFFFEC22 8, 16, 32

Wait state control register

WCR

R/W

H'FFFF

H'FFFFEC24 8, 16, 32

RAM emulation register

RAMER

R/W

H'0000

H'FFFFEC26 8, 16, 32

Note:

In register access, three cycles are required for byte access and word access, and six

cycles for longword access.

8.1.5

Address Map

Figure 8.2 shows the address format used by the SH7052F/SH7053F/SH7054F.

A31 to A24

A23, A22

A21

Output address:

Output from the address pins

Space selection:

Not output externally; used to select the type of space

On-chip ROM space or CS0 to CS3 space when 00000000 (H'00)

Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE)

On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)

CS space selection:

Decoded, outputs

CS0 to CS3 when A31 to A24 = 00000000

Figure 8.2 Address Format

This chip uses 32-bit addresses:

• Bits A31 to A24 are used to select the type of space and are not output externally.

• Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the

corresponding areas when bits A31 to A24 are 00000000.

• A21 to A0 are output externally.

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