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SH7052 Datasheet(PDF) 141 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 141 Page - Renesas Technology Corp |
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141 / 919 page  115 Section 8 Bus State Controller (BSC) 8.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the chip without external circuitry, simplifying system design and enabling high-speed data transfer to be achieved in a compact system. 8.1.1 Features The BSC has the following features: • Address space is divided into four spaces A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum 4 Mbytes for on-chip ROM disabled mode, for address space CS0 A maximum linear 4 Mbytes for each of address spaces CS1 to CS3 Bus width can be selected for each space (8 or 16 bits) Wait states can be inserted by software for each space Wait state insertion with WAIT pin in external memory space access Outputs control signals for each space according to the type of memory connected • On-chip ROM and RAM interfaces On-chip ROM and RAM access of 32 bits in 1 state |
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