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SH7052 Datasheet(PDF) 138 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 138 Page - Renesas Technology Corp

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7.5
Usage Notes
7.5.1
Simultaneous Fetching of Two Instructions
Two instructions may be simultaneously fetched from on-chip memory. If a break condition is set
on the second of these two instructions but the contents of the UBC break condition registers are
changed so as to alter the break condition immediately after the first of the two instructions is
fetched, a user break interrupt will still occur when the second instruction is fetched.
7.5.2
Instruction Fetch at Branches
When a conditional branch instruction or TRAPA instruction causes a branch, instructions are
fetched and executed as follows:
1. Conditional branch instruction, branch taken: BT, BF
TRAPA instruction, branch taken: TRAPA
Instruction fetch order:
Branch instruction fetch
→ next instruction overrun fetch →
overrun fetch of instruction after next
→ branch destination
instruction fetch
Instruction execution order: Branch instruction execution
→ branch destination instruction
execution
2. When branching with a delayed conditional instruction: BT/S and BF/S instructions
Instruction fetch order:
Branch instruction fetch
→ next instruction fetch (delay slot) →
overrun fetch of instruction after next
→ branch destination
instruction fetch
Instruction execution order: Branch instruction execution
→ delay slot instruction execution
→ branch destination instruction execution
When a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination will be fetched after the next instruction or the one after that performs an overrun
fetch. However, because the instruction that is the object of the break first breaks after a definite
instruction fetch and execution, the kind of overrun fetch instructions noted above do not become
objects of a break. If data access breaks are also included with instruction fetch breaks as break
conditions, a break occurs because the instruction overrun fetch is also regarded as becoming a
data break.



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