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SH7052 Datasheet(PDF) 149 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 149 Page - Renesas Technology Corp |
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149 / 919 page ![]() 123 • Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 1: A1SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size (Initial value) • Bit 0—CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 0: A0SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size (Initial value) Note: A0SZ is valid only in on-chip ROM enabled mode. In on-chip ROM disabled mode, the CS0 space bus size is specified by the mode pin. 8.2.2 Bus Control Register 2 (BCR2) Bit: 15 14 13 12 11 10 9 8 IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00 Initial value: 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 CW3 CW2 CW1 CW0 SW3 SW2 SW1 SW0 Initial value: 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS signal assert extension of each CS space. BCR2 is initialized to H'FFFF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. • Bits 15 to 8—Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. The idle cycles to be inserted comply with |
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