SH7052 datasheet(150/919 Pages) RENESAS

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the area specification of the previous access

. Refer to section 8.4, Waits between Access

Cycles, for details.

IW31 and IW30 specify the idle between cycles for CS3 space; IW21 and IW20 specify the

idle between cycles for CS2 space; IW11 and IW10 specify the idle between cycles for CS1

space and IW01 and IW00 specify the idle between cycles for CS0 space.

Bit 15: IW31

Bit 14: IW30

Description

No CS3 space idle cycle

Inserts one idle cycle

Inserts two idle cycles

Inserts three idle cycles

(Initial value)

Bit 13: IW21

Bit 12: IW20

Description

No CS2 space idle cycle

Inserts one idle cycle

Inserts two idle cycles

Inserts three idle cycles

(Initial value)

Bit 11: IW11

Bit 10: IW10

Description

No CS1 space idle cycle

Inserts one idle cycle

Inserts two idle cycles

Inserts three idle cycles

(Initial value)

Bit 9: IW01

Bit 8: IW00

Description

No CS0 space idle cycle

Inserts one idle cycle

Inserts two idle cycles

Inserts three idle cycles

(Initial value)

• Bits 7 to 4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The

continuous access idle specification makes insertions to clearly delineate the bus intervals by

once negating the

CSn signal when performing consecutive accesses to the same CS space.

When a write immediately follows a read, the number of idle cycles inserted is the larger of the

two values specified by IW and CW. Refer to section 8.4, Waits between Access Cycles, for

details.

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