R8C16 datasheet(45/279 Pages) RENESAS

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R8C/16 Group, R8C/17 Group

6. Voltage Detection Circuit

Rev.2.10

Jan 19, 2006

Page 32 of 254

REJ09B0169-0210

6.2

Voltage Monitor 1 Reset

Table 6.2 lists the Setting Procedure of Voltage Monitor 1 Reset Associated Bit and Figure 6.7 shows

the Operating Example of Voltage Monitor 1 Reset. When using the voltage monitor 1 reset to exit stop

mode, set the VW1C1 bit in the VW1C register to “1” (digital filter disabled).

NOTES:

1. When the VW1C0 bit is set to “0” (disabled), procedures 3, 4 and 5 can be executed simultaneously

(with 1 instruction).

Figure 6.7

Operating Example of Voltage Monitor 1 Reset

Table 6.2

Setting Procedure of Voltage Monitor 1 Reset Associated Bit

Procedure

When Using Digital Filter

When Not Using Digital Filter

Set the VCA26 bit in the VCA2 register to “1” (voltage detection 1 circuit enabled)

Wait for td(E-A)

3(1)

Select the sampling clock of the digital filter

by the VW1F0 to VW1F1 bits in the VW1C

Set the VW1C7 bit in the VW1C register to

“1”

4(1)

Set the VW1C1 bit in the VW1C register to

“0” (digital filter enabled).

Set the VW1C1 bit in the VW1C register to

“1” (digital filter disabled)

5(1)

Set the VW1C6 bit in the VW1C register to “1” (voltage monitor 1 reset mode)

Set the VW1C2 bit in the VW1C register to “0”

Set the CM14 bit in the CM1 register to “0”

(low-speed on-chip oscillator on)

−

Wait for the sampling clock of the digital

filter x 4 cycles

− (no wait time)

Set the VW1C0 bit in the VW1C register to “1” (enables voltage monitor 1 reset)

Vdet1

(Typ. 2.85V)

Internal Reset Signal

VCC

The above applies to the following conditions.

• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)

• VW1C0 bit in VW1C register = 1 (enables voltage monitor 1 reset )

• VW1C6 bit in VW1C register = 1 (voltage monitor 1 reset mode)

When the internal reset signal is held “L”, the pins, CPU and SFR are reset.

The internal reset signal is changed from “L” to “H”, the program is executed beginning with the address indicated by the

reset vector.

Refer to 4. Special Function Register (SFR) for the SFR status after reset.

fRING-S

x 32

Sampling Clock of

Digital Filter x 4 Cycles

When the VW1C1 bit is set

to “0” (digital filter enabled)

Internal Reset Signal

When the VW1C1 bit is set

to “1” (digital filter disabled)

and the VW1C7 bit is set

to “1”

fRING-S

x 32

VW1C1 and VW1C7 : Bits in VW1C Register

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