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SH7708 Datasheet(PDF) 261 Page - Renesas Technology Corp |
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SH7708 Datasheet(HTML) 261 Page - Renesas Technology Corp |
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261 / 633 page ![]() 243 Basic Timing: Figure 10.15 shows the basic timing for DRAM access is 3 cycles. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and Tc2 the read data latch cycle. CKIO RD/ WR D31 to D0 (read) D31 to D0 (write) RAS CASxx BS CS2 or CS3 A25 to A16 A15 to A0 Tr Tc1 Tc2 (Tpc) Figure 10.15 Basic Timing for DRAM Access |
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