SH7764 datasheet(49/1752 Pages) RENESAS

49 / 1752 page

Rev. 1.00 Nov. 22, 2007 Page xlix of lvi

Table 11.11

16-Bit External Device/Little-Endian Access and Data Alignment

(Areas 0 and 3).................................................................................................. 310

Table 11.12

8-Bit External Device/Little-Endian Access and Data Alignment

(Areas 0 and 3).................................................................................................. 311

Table 11.13

32-Bit External Device/Big-Endian Access and Data Alignment

(Areas 1 and 2).................................................................................................. 312

Table 11.14

32-Bit External Device/Little-Endian Access and Data Alignment

(Areas 1 and 2).................................................................................................. 313

Table 11.15

64-Bit External Device/Big-Endian Access and Data Alignment

(Areas 1 and 2).................................................................................................. 314

Table 11.16

64-Bit External Device/Little-Endian Access and Data Alignment

(Areas 1 and 2).................................................................................................. 315

Table 11.17

Supported Commands for SDRAM .................................................................. 324

Table 11.18

SDRAM Bus Widths and Address Multiplexing

(External Bus Width is 32 Bits) ........................................................................ 327

Table 11.19

Correspondence between Linear Addresses and Tiled Memory Addresses...... 355

Section 12 Direct Memory Access Controller (DMAC)

Table 12.1

Pin Configuration.................................................................................................. 361

Table 12.2

Table 12.3

State of Registers in Each Operating Mode .......................................................... 364

Table 12.4

Transfer Request Sources ..................................................................................... 383

Table 12.5

Setting External Request Mode with RS Bits ....................................................... 384

Table 12.6

Selecting External Request Detection with DL, DS Bits ...................................... 385

Table 12.7

Selecting External Request Detection with DO Bit .............................................. 385

Table 12.8

Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0] ........... 386

Table 12.9

DMA Transfer Matrix in Auto-Request Mode ..................................................... 396

Table 12.10

DMA Transfer Matrix in External Request Mode (Only Channels 0 and 1) .... 396

Table 12.11

DMA Transfer Matrix in On-Chip Peripheral module Request Mode.............. 397

Section 13 Interrupt Controller (INTC)

Table 13.1

Interrupt Types...................................................................................................... 412

Table 13.2

INTC Pin Configuration ....................................................................................... 414

Table 13.3

INTC Register Configuration ............................................................................... 415

Table 13.4

Table 13.5

Interrupt Request Sources and INT2PRI0 to INT2PRI12..................................... 431

Table 13.6

Interrupt Exception Handling and Priority............................................................ 458

Table 13.7

Interrupt Response Time....................................................................................... 465

Table 13.8

Switching Sequence of IRQ1 and IRQ0 Pin Function.......................................... 467

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