32182 datasheet(19/755 Pages) RENESAS

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CHAPTER 9 DMAC

9.1 Outline of the DMAC ------------------------------------------------------------------------------------------------------ 9-2

9.2 DMAC Related Registers ------------------------------------------------------------------------------------------------ 9-4

9.2.1

DMA Channel Control Registers --------------------------------------------------------------------------- 9-6

9.2.2

DMA Software Request Generation Registers ---------------------------------------------------------- 9-18

9.2.3

DMA Source Address Registers ---------------------------------------------------------------------------- 9-19

9.2.4

DMA Destination Address Registers ---------------------------------------------------------------------- 9-20

9.2.5

DMA Transfer Count Registers ----------------------------------------------------------------------------- 9-21

9.2.6

DMA Interrupt Related Registers --------------------------------------------------------------------------- 9-22

9.3 Functional Description of the DMAC ---------------------------------------------------------------------------------- 9-27

9.3.1

DMA Transfer Request Sources ---------------------------------------------------------------------------- 9-27

9.3.2

DMA Transfer Processing Procedure --------------------------------------------------------------------- 9-33

9.3.3

Starting DMA ---------------------------------------------------------------------------------------------------- 9-34

9.3.4

DMA Channel Priority ----------------------------------------------------------------------------------------- 9-34

9.3.5

Gaining and Releasing Control of the Internal Bus ---------------------------------------------------- 9-34

9.3.6

Transfer Units --------------------------------------------------------------------------------------------------- 9-35

9.3.7

Transfer Counts ------------------------------------------------------------------------------------------------- 9-35

9.3.8

Address Space -------------------------------------------------------------------------------------------------- 9-35

9.3.9

Transfer Operation --------------------------------------------------------------------------------------------- 9-35

9.3.10

End of DMA and Interrupt ------------------------------------------------------------------------------------ 9-37

9.3.11

Each Register Status after Completion of DMA Transfer -------------------------------------------- 9-37

9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------ 9-38

CHAPTER 10 MULTIJUNCTION TIMERS

10.1 Outline of Multijunction Timers --------------------------------------------------------------------------------------- 10-2

10.2 Common Units of Multijunction Timers ----------------------------------------------------------------------------- 10-8

10.2.1

MJT Common Unit Register Map -------------------------------------------------------------------------- 10-9

10.2.2

Prescaler Unit -------------------------------------------------------------------------------------------------- 10-10

10.2.3

Clock Bus and Input/Output Event Bus Control Unit ------------------------------------------------- 10-11

10.2.4

Input Processing Control Unit ------------------------------------------------------------------------------ 10-15

10.2.5

Output Flip-flop Control Unit -------------------------------------------------------------------------------- 10-21

10.2.6

Interrupt Control Unit ----------------------------------------------------------------------------------------- 10-26

10.3 TOP (Output-Related 16-Bit Timer) --------------------------------------------------------------------------------- 10-43

10.3.1

Outline of TOP -------------------------------------------------------------------------------------------------- 10-43

10.3.2

Outline of Each Mode of TOP ------------------------------------------------------------------------------- 10-45

10.3.3

TOP Related Register Map ---------------------------------------------------------------------------------- 10-47

10.3.4

TOP Control Registers ---------------------------------------------------------------------------------------- 10-49

10.3.5

TOP Counters (TOP0CT–TOP10CT) --------------------------------------------------------------------- 10-54

10.3.6

TOP Reload Registers (TOP0RL–TOP10RL) ----------------------------------------------------------- 10-55

10.3.7

TOP Correction Registers (TOP0CC–TOP10CC) ----------------------------------------------------- 10-56

10.3.8

TOP Enable Control Registers ------------------------------------------------------------------------------ 10-57

10.3.9

Operation in TOP Single-shot Output Mode (with Correction Function) -------------------------- 10-59

10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) -------------- 10-65

10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) --------------------- 10-70

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