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TDA9109N Datasheet(PDF) 18 Page - STMicroelectronics

Part # TDA9109N
Description  LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PDF  32 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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TDA9109N Datasheet(HTML) 18 Page - STMicroelectronics

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II.2 - PLL1
The PLL1 consists of a phase comparator, an
external filter and a voltage-controlled oscillator
(VCO). The phase comparator is a ”phase fre-
quency” type designed in CMOS technology. This
kind of phase detector avoids locking on wrong
frequencies. It is followed by a ”charge pump”,
composed of two current sources : sunk and sour-
ced (typically I = 1mA when locked and I = 140
µA
whenunlocked).This differencebetweenlock/unlock
allows smooth catching of the horizontal frequency
by PLL1. This effect is reinforced by an internal
original slow down system when PLL1 is locked,
avoiding the horizontal frequency changing too
quickly. The dynamic behaviour of PLL1 is fixed by
an external filter which integrates the current of the
charge pump. A ”CRC” filter is generally used
(see Figure 7).
The PLL1 is internally inhibited during extracted
vertical sync (if any) to avoid taking in account
missing pulses or wrong pulses on phase compa-
rator.The inhibition is done by a switch located
between the charge pump and the filter (see Fig-
7
PLL1F
1
µF
4.7
µF
1.8k
Ω
Figure 7
OPERATING DESCRIPTION (continued)
ure 8). The VCO uses an external RC network. It
delivers a linear sawtooth obtained by the charge
and the discharge of the capacitor, with a current
proportional to the current in the resistor. The typi-
cal thresholds of the sawtooth are 1.6V and 6.4V.
The control voltage of the VCO is between 1.33V
and 6V (see Figure 9). The theorical frequency
range of this VCO is in the ratio of 1 to 4.5.
The effective frequency range has to be smaller
(1 to 4.2) due to clamp intervention on the filter
lowest value.
6
7
Loop
Filter
R0
1.6V
6.4V
5
C0
6.4V
1.6V
0 0.875T
H TH
RS
FLIP FLOP
(1.3V < V
< 6V)
7
I0
2
4 I0
I
0
Figure 9 : Details of VCO
LOCKDET
COMP1
INPUT
INTERFACE
H/HVIN
High
CHARGE
PUMP
Low
PLL
INHIBITION
VCO
76
5
PLL1F
R0
C0
PHASE
ADJUST
E2
I2C
HPOS
Adj.
OSC
Tramext
Tramext
I2C
Forced
Frequency
Lock/Unlock
Status
8
HPOSITION
1
Figure 8 : Block Diagram
TDA9109/N
18/32



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