DSP56724 datasheet(13/48 Pages) FREESCALE

13 / 48 page

Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

Figure 10 shows external interrupt timing (negative edge-triggered).

Figure 10. External Interrupt Timing (Negative Edge-Triggered)

Figure 11 shows MODE select set-up and hold time diagram.

Figure 11. MODE Select Set-Up and Hold Time

1.2

Module-Level Specifications

Table 8 provides a quick reference to the subsections of this section.

Table 8. Module-Level Specifications

For

See

Section 1.2.1, “Serial Host Interface SPI Protocol Timing”

on page 4

Section 1.2.2, “Serial Host Interface (SHI) I2C Protocol Timing”

on page 6

Section 1.2.3, “Programming the SHI I2C Serial Clock”

on page 6

Section 1.2.4, “Enhanced Serial Audio Interface Timing”

on page 7

Section 1.2.5, “GPIO Timing”

on page 28

Section 1.2.6, “JTAG Timing”

on page 29

Section 1.2.7, “Watchdog Timer Timing”

on page 31

Section 1.2.8, “S/PDIF Timing”

on page 32

Section 1.2.9, “EMC Timing Specifications—DSP56724”

on page 33

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

RESET

MODA, MODB,

MODC, MODD,

PINIT

VIH

IRQA, IRQB,

IRQC,IRQD, NMI

VIH

VIL

DSP56724 Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc

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