AD7682 datasheet(21/28 Pages) AD

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AD7949

Rev. A | Page 21 of 28

DIGITAL INTERFACE

The AD7949 uses a simple 4-wire interface and is compatible

with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for

example, Blackfin® ADSP-BF53x, SHARC®, ADSP-219x, and

ADSP-218x.

The interface uses the CNV, DIN, SCK, and SDO signals and

allows CNV, which initiates the conversion, to be independent

of the readback timing. This is useful in low jitter sampling or

simultaneous sampling applications.

A 14-bit register, CFG[13:0], is used to configure the ADC for

the channel to be converted, the reference selection, and other

components, which are detailed in the Configuration Register,

CFG, section.

When CNV is low, reading/writing can occur during conversion,

acquisition, and spanning conversion (acquisition plus conversion),

as detailed in the following sections. The CFG word is updated

on the first 14 SCK rising edges, and conversion results are read

back on the first 13 (or 14 if busy mode is selected) SCK falling

edges. If the CFG readback is enabled, an additional

14 SCK falling edges are required to read back the CFG word

associated with the conversion results with the CFG MSB

following the LSB of the conversion result.

A discontinuous SCK is recommended because the part is

selected with CNV low and SCK activity begins to write a new

configuration word and clock out data.

Note that in the following sections, the timing diagrams

indicate digital activity (SCK, CNV, DIN, SDO) during the

conversion. However, due to the possibility of performance

degradation, digital activity should occur only prior to the safe

data reading/writing time, tDATA, because the AD7949 provides

error correction circuitry that can correct for an incorrect bit

during this time. From tDATA to tCONV, there is no error

correction and conversion results may be corrupted. The user

should configure the AD7949 and initiate the busy indicator (if

desired) prior to tDATA. It is also possible to corrupt the sample

by having SCK or DIN transitions near the sampling instant.

Therefore, it is recommended to keep the digital pins quiet for

approximately 30 ns before and 10 ns after the rising edge of

CNV, using a discontinuous SCK whenever possible to avoid

any potential performance degradation.

Reading/Writing During Conversion, Fast Hosts

When reading/writing during conversion (n), conversion

results are for the previous (n − 1) conversion, and writing the

CFG is for the next (n + 1) acquisition and conversion.

After the CNV is brought high to initiate conversion, it must be

brought low again to allow reading/writing during conversion.

Reading/writing should only occur up to tDATA and, because this

time is limited, the host must use a fast SCK.

The SCK frequency required is calculated by

DATA

Edges

SCK

Number

SCK

≥

The time between tDATA and tCONV is a safe time when digital

activity should not occur, or sensitive bit decisions may be

corrupt.

Reading/Writing During Acquisition, Any Speed Hosts

When reading/writing during acquisition (n), conversion

results are for the previous (n − 1) conversion, and writing is for

the (n + 1) acquisition.

For the maximum throughput, the only time restriction is that

the reading/writing take place during the tACQ (min) time. For

slow throughputs, the time restriction is dictated by throughput

required by the user, and the host is free to run at any speed.

Thus for slow hosts, data access must take place during the

acquisition phase.

Reading/Writing Spanning Conversion, Any Speed Host

When reading/writing spanning conversion, the data access

starts at the current acquisition (n) and spans into the

conversion (n). Conversion results are for the previous (n − 1)

conversion, and writing the CFG is for the next (n + 1) acquisition

and conversion.

Similar to reading/writing during conversion, reading/writing

should only occur up to tDATA. For the maximum throughput,

the only time restriction is that reading/writing take place

during the tACQ (min) + tDATA time.

For slow throughputs, the time restriction is dictated by the

user’s required throughput, and the host is free to run at any

speed. Similar to the reading/writing during acquisition, for

slow hosts, the data access must take place during the

acquisition phase with additional time into the conversion.

Note that data access spanning conversion requires the CNV to

be driven high to initiate a new conversion, and data access is

not allowed when CNV is high. Thus, the host must perform

two bursts of data access when using this method.

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