AD7682/AD7689

Rev. 0 | Page 23 of 28

The register can be written to during conversion, during

acquisition, or spanning acquisition/conversion and is updated at

the end of conversion, tCONV (max). There is always a one deep

delay when writing CFG. Note that, at power up, the CFG is

undefined and two dummy conversions are required to update

the register. To preload the CFG with a factory setting, hold

DIN high for two conversions. Thus CFG[13:0] = 0x3FFF. This

sets the AD7682/AD7689 for

•

IN[7:0] unipolar referenced to GND, sequenced in order

•

Full bandwidth for one-pole filter

•

Internal reference/temperature sensor disabled, buffer

enabled

•

No readback of CFG

Table 9 summarizes the configuration register bit details. See

the Theory of Operation section for more details.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CFG

INCC

INCC

INCC

INx

INx

INx

BW

REF

REF

REF

SEQ

SEQ

RB

Table 9. Configuration Register Description

Bit(s)

Name

Description

[13]

CFG

Configuration update.

0 = Keep current configuration settings.

1 = Overwrite contents of register.

[12:10]

INCC

Input channel configuration. Selection of pseudobipolar, pseudodifferential, pairs, single-ended or temperature sensor. Refer to

the

Input Configurations section.

Bit 12

Bit 11

Bit 10

Function

0

0

X

0

1

0

0

1

1

Temperature sensor.

1

0

X

Unipolar differential pairs; INx− referenced to GND ± 0.1 mV.

1

1

0

Unipolar, IN0 to IN7 referenced to COM = GND ± 0.1 V (GND sense).

1

1

1

Unipolar, IN0 to IN7 referenced to GND.

[9:7]

INx

Input channel selection in binary fashion.

AD7682

AD7689

Bit 9

Bit 8

Bit 7

Channel

Bit 9

Bit 8

Bit 7

Channel

0

0

X

IN0

0

0

0

IN0

0

1

X

IN1

0

0

1

IN1

1

0

X

IN2

…

…

…

1

1

X

IN3

1

1

1

IN7

[6]

BW

Select bandwidth for low-pass filter. Refer to the

Selectable Low Pass Filter section.

0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughout must be reduced to ¼

also.

1 = Full BW.

[5:3]

REF

Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.

Refer to the

Voltage Reference Output/Input section.

Bit 5

Bit 4

Bit 3

Function

0

0

0

Internal reference, REF = 2.5 V output.

0

0

1

Internal reference, REF = 4.096 V output.

0

1

0

External reference, temperature enabled.

0

1

1

External reference, internal buffer, temperature enabled.

1

1

0

External reference, temperature disabled.

1

1

1

External reference, internal buffer, temperature disabled.

[2:1]

SEQ

Channel sequencer. Allows for scanning channels in an IN0 to INx fashion. Refer to the

Sequencer section.

Bit 2

Bit 1

Function

0

0

Disable sequencer.

0

1

Update configuration during sequence.

1

0

Scan IN0 to INx (set in CFG[9:7]), then temperature.

1

1

Scan IN0 to INx (set in CFG[9:7]).

0

RB

Read back the CFG register.

0 = Read back current configuration at end of data.

1 = Do not read back contents of configuration.