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ADV3200/ADV3201

Rev. 0 | Page 31 of 3

ON-SCREEN DISPLAY (OSD)

The ADV3200/ADV3201 features dedicated 2:1 muxes for each

of the 32 outputs that allow external video or dc levels to be

inserted and switched in with the regular input channel. The

OSD mux switches in 20 ns, allowing for information such as

text or other picture-on-picture signals to be displayed. The

OSDSxx pins are the control switches used to switch each

corresponding OSD mux (high = OSD, low = regular input).

Pulling OSDSxx high switches the signal that appears at the

OSDxx input to the corresponding output. Setting OSDSxx

low switches the signal at INxx to the corresponding output.

This switching can be done on a pixel-by-pixel basis for each

scan line, and in this way any video signal, including graphics,

characters, or text, can be inserted to be displayed at the output.

The OSD signal must be synchronized to the incoming video

signal that it is switching between; therefore, the OSDS signal

must be correctly timed in order to correctly place the OSD

signal on the horizontal line. In addition, the OSDxx inputs do

not have the sync-tip clamp feature described in the previous

section, so the dc level must be set appropriately at the OSDxx

input.

DECOUPLING

The signal path of the ADV3200/ADV3201 is based on high

open-loop gain amplifiers with negative feedback. Dominant-

pole compensation is used on chip to stabilize these amplifiers

over the range of expected applied swing and load conditions.

To guarantee this designed stability, proper supply decoupling is

necessary. Signal-generated currents must return to their sources

through low impedance paths at all frequencies in which there

is still loop gain (up to 300 MHz at a minimum). A wideband

parallel capacitor arrangement is necessary to properly decouple

the ADV3200/ADV3201.

The VREF and VCLAMP pins should be considered reference

pins, not power supply pins, because they are both inputs to

on-chip buffers. Because the VREF pin is used as a ground

reference in the ADV3200/ADV3201, care must be taken to

produce a low noise VREF source over the entire range of

frequencies of interest.

POWER DISSIPATION

Calculation of Power Dissipation

AMBIENT TEMPERATURE (°C)

TJ = 150°C

Figure 104. Maximum Die Power Dissipation vs. Ambient Temperature

The curve in Figure 104 is calculated from

AMBIENT

MAX

JUNCTION

MAX

−

(1)

For example, if the ADV3200/ADV3201 is enclosed in an environ-

ment at 45°C (TA), the total on-chip dissipation under all load

and supply conditions must not be allowed to exceed 6.5 W.

When calculating on-chip power dissipation, it is necessary to

include the rms current being delivered to the load, multiplied

by the rms voltage drop on the ADV3200/ADV3201 output

devices. For a sinusoidal output, the on-chip power dissipation

due to the load can be approximated by

PD,OUTPUT = (VPOS – VOUTPUT,RMS) × IOUTPUT,RMS

(2)

For a nonsinusoidal output, the power dissipation should be

calculated by integrating the on-chip voltage drop multiplied

by the load current over one period.

The user can subtract the quiescent current for the Class AB

output stage when calculating the loaded power dissipation. For

each output stage driving a load, subtract the quiescent power

according to

PDQ,OUTPUT = (VPOS – VNEG) × IOUTPUT,QUIESCENT

(3)

where IOUTPUT,QUIESCENT = 0.95 mA for each single-ended output pin.

For each disabled output, the quiescent power supply current in

VPOS and VNEG drops by approximately 4 mA.

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