ADV3201ASWZ datasheet(28/36 Pages) AD

28 / 36 page

ADV3200/ADV3201

Rev. 0 | Page 28 of

In addition to a receiver, each input also has a sync-tip clamp

for use in ac-coupled applications. All clamps are enabled or

disabled according to the first serial data bit shifted in during

programming logic. When enabled, the clamp forces the lowest

input voltage to the voltage on the VCLAMP pin. The VCLAMP

pin is common to the entire chip and needs to be driven from a

low impedance source to avoid crosstalk.

IN00

VPOS

VNEG

VCLAMP

5µA

TO INPUT

RECEIVER

OFF-CHIP

CAPACITOR

Figure 98. Conceptual Diagram of Sync-Tip Clamp in an

AC-Coupled Application

The output stage of the ADV3200/ADV3201 is designed for low

differential gain and phase error when driving composite video

signals. It also provides slew current for fast pulse response

when driving component video signals.

The outputs of the ADV3200/ADV3201 can be disabled to

minimize on-chip power dissipation. When disabled, a series of

internal amplifiers drives internal nodes such that a wideband

high impedance is presented at the disabled output, even when

the output bus is under large signal swings. (In the ADV3201,

there is 4 kΩ of resistance terminated to the VREF voltage by

the reference buffer.) This high impedance allows multiple ICs

to be bussed together without additional buffering.

Care must be taken to reduce output capacitance, which results

in more overshoot and frequency domain peaking. In addition,

when the outputs are disabled and driven externally, the voltage

applied to them must not exceed the valid output swing range

for the ADV3200/ADV3201 in order to keep these internal

amplifiers in their linear range of operation. Applying excess

voltage to the disabled outputs can cause damage to the

ADV3200/ADV3201 and should be avoided (see the Absolute

Maximum Ratings section for guidelines).

The internal connection of the ADV3200/ADV3201 is con-

trolled by a serial logic interface. Serial loading into a first rank

of latches preprograms each output. A global update signal

(UPDATE) moves the programming data into the second rank

of latches, simultaneously updating all outputs. A serial output

pin (DATA OUT) allows devices to be daisy chained for single-

pin programming of multiple ICs. A reset pin is available to

avoid bus conflicts by disabling all outputs. This reset clears

both the first and second rank of latches.

The ADV3200 can operate on a single 5 V supply, powering

both the signal path (with the VPOS/VNEG supply pins) and

the control logic interface (with the DVCC/DGND supply

pins). However, in order to easily interface to ground referenced

video signals, split supply operation is possible with ±2.5 V.

(The ADV3201 is intended to operate on ±3.3 V.) In the case of

split supplies, a flexible logic interface allows the control logic

supplies (DVCC/DGND) to be run off 3.3 V/0 V to 5 V/0 V

while the core remains on split supplies.

ADV3201ASWZ Datasheet(PDF) 28 Page - Analog Devices

ADV3201ASWZ Datasheet(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL