MPC5565 datasheet(51/54 Pages) FREESCALE

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Revision History for the MPC5565 Data Sheet

MPC5565 Microcontroller Data Sheet, Rev. 2.0

Freescale Semiconductor

Table 17 Pad AC Specifications:

• Footnote 1, Changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’

• Footnote 3, Changed from ‘Out delay. . .’ to ‘The output delay. . .’,

• Changed from ‘ Add a maximum of one system clock to the output delay to get the output delay with respect to

the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one system

clock to the output delay.’

• Footnote 4: Changed ‘Delay’ to ‘The output delay.’

Table 19 Reset and Configuration Pin Timing

• Footnote 1: Removed VDD =1.35–1.65.

Table 20 JTAG Pin AC Electrical Characteristics

• Footnote 1: Removed VDD =1.35–1.65; and VDD33 and VDDSYN = 3.0–3.6 V.

Table 22 Bus Operation Timing:

• Specifications 5 and 6. Changed EBTS to SIU_ECCR[EBTS].

• Specifications 7 and 8: Removed CS[0:3], BDIP, OE, and WE/BE[0:3] because these pins are not used on the

input signal to CLKOUT.

• Specification 7: Removed CAL_CS[0, 2:3], CAL_OE, and CAL_WE/BE[0:1] because these pins are not used on

the input signal to CLKOUT.

• Specification 8: Added to the beginning of the calibration section: CLKOUT positive edge to input signal invalid

(hold time). Removed CAL_CS[0, 2:3], CAL_OE, and CAL_WE/BE[0:1] because these pins are not used on the

input signal to CLKOUT.

• Footnote 1: Deleted VDD = 1.35–1.65; and VDD33 and VDDSYN = 3.0–3.6 V.

• Added footnote 2: “Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed

including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow

for 112 MHz system clock + 2% FM; and 135 MHz parts allow for 132 MHz system clock + 2% FM.’

• Added footnotes 5, 6, and 7, one each for the DATA[0:31], TEA, and WE/BE[0:3] signals in the table: Due to pin

limitations, the DATA[16:31], TEA, and WE/BE[2:3] signals are not available on the 324 package.

• Footnote 8: Changed EBTS to SIU_ECCR[EBTS].

Table 23 External Interrupt Timing (IRQ Signals)

• Footnote 1: Removed VDD = 1.35–1.65 V; changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.

Table 24 eTPU Timing

• Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.

Table 25 eMIOS Timing

• Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.

Table 26 DSPI Timing:

• Specification 1: SCK cycle time. Changed 80 MHz column, Min.: from 25 to 24.4; 112 MHz columns, Min.: from

17.9 to 17.5, Max: from 2.0 to 2.1; 132 MHz columns, Min.: from 15.2 to 14.8, Max: from 1.7 to 1.8.

• Footnote 1, changed ‘VDDEH = 3.0–5.5 V;’ to ‘VDDEH = 3.0–5.25 V;’

• Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum

speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;

114 MHz parts allow for 112 MHz system clock + 2% FM, 135 MHz parts allow for 132 MHz system clock + 2%

FM.

Table 27 EQADC SSI Timing Characteristics

• Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.

Table 29. MPC5565 Changes Between Rev. 1.0 and 2.0 (continued)

Location

Description of Changes

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