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OPA653IDBVT Datasheet(PDF) 4 Page - Texas Instruments

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Part # OPA653IDBVT
Description  Wideband, Fixed Gain, JFET-Input AMPLIFIER
PDF  19 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

OPA653IDBVT Datasheet(HTML) 4 Page - Texas Instruments

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TYPICAL CHARACTERISTICS
OPA653
SBOS348 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±6 V (continued)
At G = +2 V/V, RL = 100 Ω, and TA = +25°C, unless otherwise noted.
OPA653
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
POWER SUPPLY
Specified Operating Voltage
TA = –40°C to +85°C
±3.5
±6
±6.5
V
B
Quiescent Current
TA = +25°C
30.5
32
33.5
mA
A
TA = –40°C to +85°C
28.3
35.7
mA
B
Power-Supply Rejection Ratio
TA = +25°C, ±VS = 5.5 V to 6.5 V
62
66
dB
A
TA = –40°C to +85°C, ±VS = 5.5 V to 6.5 V
60
64
dB
B
THERMAL CHARACTERISTICS
Specified Operating Range
–40
+85
°C
C
DBV and DRB Packages
Thermal Resistance,
θ
JA
Junction-to-ambient
DBV
SOT23-5
105
°C/W
C
DRB
VSON-8
55
°C/W
C
Table of Graphs
TITLE
FIGURE
Small-Signal Frequency Response
VO = 200 mVPP
Figure 1
Noninverting Large-Signal Frequency Response
Gain = +2 V/V
Figure 2
Inverting Large-Signal Frequency Response
Gain = –1 V/V
Figure 3
Input-Referred Voltage and Current Noise Spectral Density
Figure 4
Noninverting Transient Response
0.5-V Step
Figure 5
Inverting Transient Response
0.5-V Step
Figure 6
Harmonic Distortion vs Frequency
Figure 7, Figure 8
Harmonic Distortion vs Load
Figure 9
Harmonic Distortion vs Output Voltage
Figure 10
Harmonic Distortion vs ±Supply Voltage
Figure 11
Two-Tone, Second- and Third-Order Intermodulation Distortion vs Frequency
Figure 12
Noninverting Overdrive Recovery
Gain = +2 V/V
Figure 13
Inverting Overdrive Recovery
Gain = –1 V/V
Figure 14
Power-Supply Rejection Ratio vs Frequency
Figure 15
Frequency Response vs Capacitive Load
Figure 16
Recommended RISO vs Capacitive Load
Figure 17
Closed-Loop Output Impedance vs Frequency
Figure 18
Slew Rate vs VOUT Step
Figure 19
Output Voltage Swing vs RLOAD
Figure 20
4
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA653



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