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CS5346 Datasheet(PDF) 21 Page - Cirrus Logic |
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CS5346 Datasheet(HTML) 21 Page - Cirrus Logic |
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21 / 40 page ![]() DS861PP1 21 CS5346 5. APPLICATIONS 5.1 Recommended Power-Up Sequence 1. Hold RST low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset to its default settings. 2. Bring RST high. The device will remain in a low power state with the PDN bit set by default. The control port will be accessible. 3. The desired register settings can be loaded while the PDN bit remains set. 4. Clear the PDN bit to initiate the power-up sequence. 5.2 System Clocking The CS5346 will operate at sampling frequencies from 8 kHz to 200 kHz. This range is divided into three speed modes as shown in Table 1. 5.2.1 Master Clock MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked out of the device. The FM bits (See “Func- tional Mode (Bits 7:6)” on page 31.) and the MCLK Freq bits (See “MCLK Frequency - Address 05h” on page 32.) configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. Mode Sampling Frequency Single-Speed 8-50 kHz Double-Speed 50-100 kHz Quad-Speed 100-200 kHz Table 1. Speed Modes LRCK (kHz) MCLK (MHz) * 64x * 96x 128x 192x 256x 384x 512x 768x 1024x 32 - --- 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 - --- 11.2896 16.9344 22.5792 33.8680 45.1584 48 - --- 12.2880 18.4320 24.5760 36.8640 49.1520 64 - - 8.1920 12.2880 16.3840 24.5760 32.7680 - - 88.2 - - 11.2896 16.9344 22.5792 33.8680 45.1584 - - 96 - - 12.2880 18.4320 24.5760 36.8640 49.1520 - - 128 8.1920 12.2880 16.3840 24.5760 32.7680 - - - - 176.4 11.2896 16.9344 22.5792 33.8680 45.1584 - - - - 192 12.2880 18.4320 24.5760 36.8640 49.1520 - - - - Mode QSM DSM SSM * Only available in master mode. Table 2. Common Clock Frequencies |
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