CS5581

22

DS796PP1

3/25/08

14:34

Figure 16 illustrates the noise floor of the converter from 0.1 Hz to 100 kHz. While the plot does exhibit

some 1/f noise at lower frequencies, the noise floor is entirely free of spurious frequency content due to

digital activity inside the chip.

Figure 17 illustrates a noise histogram of 4096 samples.

-160

-140

-120

-100

-80

-60

-40

-20

0

0.1

1

10

100

1k

10k

100k

Frequency (Hz)

Shorted Input

2M Samples @ 200 kSps

16 Averages

Figure 16. Spectral Plot of Noise with Shorted Input

0

100

200

300

400

500

600

700

800

900

-8

-7

-6

-5

-4

-3

-2

-1

012

34

5678

Mean = -0.61

Std. Dev = 2.33

Output (Codes)

Figure 17. Noise Histogram (4096 Conversions)