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AT89C5122DS-RDRUM Datasheet(PDF) 41 Page - ATMEL Corporation |
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AT89C5122DS-RDRUM Datasheet(HTML) 41 Page - ATMEL Corporation |
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41 / 208 page  41 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Figure 18. PLL Programming Flow Clock Tree Architecture The clock controller outputs several different clocks as shown in Figure 19: • a clock for the CPU core • a clock for the peripherals which is used to generate the timers, watchdog, SPI, UART, and ports sampling clocks. This divided clock will be used to generate the alternate card clock. • a clock for the USB • a clock for the SCIB controller • a clock for the DC/DC converter These clocks are enabled or not depending on the power reduction mode as detailed in Section “Power Management”, page 178. These clocks are generated using four presacalers defined in the table below: PLL Programming Configure Dividers N3:0= xxxxb R3:0= xxxxb Enable PLL PLLEN= 1 PLL Locked? PLOCK= 1? Prescaler Register Reload Factor Function PR1 CKRL CKRL[0:3] CPU & Peripheral clocks PR2 SCICLK SCICLK[0:5] Smart card PR3 SCSR ALTKPS[0:1] Alternate card PR4 DCCKPS DCCKPS[3:0] DC/DC |
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