CDCE62005 datasheet(69/76 Pages) TI

69 / 76 page

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30.72 MHz

10.00 MHz

122 .88 MHz

491 .52 MHz

245 .76 MHz

30.72 MHz

10 MHz

20 log

jitter

total

SNR

πf jitter

(8)

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total

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jitter

(9)

6.02

1.76

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SNR

(10)

CDCE62005

www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008

Figure 43. CDCE62005 Jitter Cleaner Example

Clocking ADCs with the CDCE62005

High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample

clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly

implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation

trend often causes engineers working in communications system design to encounter the term clock limited

performance. Therefore, it is important to understand the impact of clock jitter on ADC performance. Equation 8

shows the relationship of data converter signal to noise ratio (SNR) to total jitter.

Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample

clock:

With respect to an ADC with N-bits of resolution, ignoring total jitter, DNL, and input noise, the following equation

shows the relationship between resolution and SNR:

Figure 44 plots Equation 8 and Equation 10 for constant values of total jitter. When used in conjunction with most

ADCs, the CDCE62005 supports a total jitter performance value of <1 ps.

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