ACS8530 datasheet(97/152 Pages) SEMTECH

97 / 152 page

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 97

www.semtech.com

ACS8530 SETS

ext_switch

Bit to enable external switching mode. When in

external switching mode, the device is only allowed

to lock to a pair of sources. If the programmed

priority of input I3 is non-zero, then the SRCSWIT pin

is High, the device will be forced to lock to input I3

regardless of the signal present on that input. If the

programmed priority of input I3 is zero, then it will

be forced to lock to input I5 instead. If the

programmed priority of input I4 is non-zero, then the

SRCSW pin is Low, the device will be forced to lock

to input I4 regardless of the signal present on that

input. If the programmed priority of input I4 is zero,

then it will be forced to lock to input I6 instead.

* The default value of this bit is dependent on the

value of the SRCSW pin at power-up.

Normal operation mode.

External source switching mode enabled. Operating

mode of the device is always forced to be “locked”

when in this mode.

PBO_freeze

Bit to control the freezing of Phase Build-out

operation. If Phase Build-out has been enabled and

there have been some source switches, then the

input-output phase relationship of the T0 DPLL is

unknown. If Phase Build-out is no longer required,

then it can be frozen. This will maintain the current

input-output phase relationship, but not allow

further Phase Build-out events to take place. Simply

disabling Phase Build-out could cause a phase shift

in the output, as the T0 DPLL re-locks the phase to

zero degrees.

Phase Build-out not frozen.

Phase Build-out frozen, no further Phase Build-out

events will occur.

PBO_en

Bit to enable Phase Build-out events on source

switching. When enabled a Phase Build-out event is

triggered every time the T0 DPLL selects a new

source- this includes exiting the Holdover or Free-

run states.

Phase Build-out not enabled. T0 DPLL locks to zero

degrees phase.

Phase Build-out enabled on source switching.

freq_monitor_soft_enable

Control to enable frequency monitoring of input

reference sources using soft frequency alarms.

Soft frequency monitor alarms disabled.

Soft frequency monitor alarms enabled.

freq_monitor_hard_enable

Control to enable frequency monitoring of input

reference sources using hard frequency alarms.

Hard frequency monitor alarms disabled.

Hard frequency monitor alarms enabled.

Address (hex):

48 (cont...)

Description

(R/W) Configuration register

controlling several input

monitoring and switching options.

Default Value

0000 0101*

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

freq_mon_clk

los_flag_on_

TDO

ultra_fast_

switch

ext_switch

PBO_freeze

PBO_en

freq_monitor_

soft_enable

freq_monitor_

hard_enable

Bit No.

Description

Bit Value

Value Description

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