MSP430F2012IPWR datasheet(13/88 Pages) TI

13 / 88 page

MSP430x20x1, MSP430x20x2, MSP430x20x3

MIXED SIGNAL MICROCONTROLLER

SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh--0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will

go into LPM4 immediately after power-up.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up

External reset

Watchdog Timer+

Flash key violation

PC out-of-range (see Note 1)

PORIFG

RSTIFG

WDTIFG

KEYV

(see Note 2)

Reset

0FFFEh

31, highest

NMI

Oscillator fault

Flash memory access violation

NMIIFG

OFIFG

ACCVIFG

(see Notes 2 and 4)

(non)-maskable,

(non)-maskable

0FFFCh

0FFFAh

0FFF8h

Comparator_A+ (MSP430x20x1 only)

CAIFG(seeNote3)

maskable

0FFF6h

Watchdog Timer+

WDTIFG

maskable

0FFF4h

Timer_A2

TACCR0 CCIFG (see Note 3)

maskable

0FFF2h

Timer_A2

TACCR1 CCIFG.

TAIFG (see Notes 2 and 3)

maskable

0FFF0h

0FFEEh

0FFECh

ADC10 (MSP430x20x2 only)

ADC10IFG (see Note 3)

maskable

SD16_A (MSP430x20x3 only)

SD16CCTL0 SD16OVIFG,

SD16CCTL0 SD16IFG

(see Notes 2 and 3)

maskable

0FFEAh

USI

(MSP430x20x2, MSP430x20x3 only)

USIIFG, USISTTIFG

(see Notes 2 and 3)

maskable

0FFE8h

I/O Port P2

(two flags)

P2IFG.6toP2IFG.7

(see Notes 2 and 3)

maskable

0FFE6h

I/O Port P1

(eight flags)

P1IFG.0toP1IFG.7

(see Notes 2 and 3)

maskable

0FFE4h

0FFE2h

0FFE0h

(see Note 5)

0FFDEh ... 0FFC0h

15 ... 0, lowest

NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h--01FFh) or from

within unused address ranges.

2. Multiple source flags

3. Interrupt flags are located in the module

4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

5. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

MSP430F2012IPWR Datasheet(PDF) 13 Page - Texas Instruments

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