MSP430F2012IPWR datasheet(15/88 Pages) TI

15 / 88 page

MSP430x20x1, MSP430x20x2, MSP430x20x3

MIXED SIGNAL MICROCONTROLLER

SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

memory organization

MSP430F200x

MSP430F201x

Memory

Main: interrupt vector

Main: code memory

Size

Flash

1KB Flash

0FFFFh--0FFC0h

0FFFFh--0FC00h

2KB Flash

0FFFFh--0FFC0h

0FFFFh--0F800h

Information memory

Size

Flash

256 Byte

010FFh -- 01000h

256 Byte

010FFh -- 01000h

RAM

Size

128 Byte

027Fh -- 0200h

128 Byte

027Fh -- 0200h

Peripherals

16-bit

8-bit

8-bit SFR

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

flash memory

The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can

perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

Flash memory has n segments of main memory and four segments of information memory (A to D) of 64

bytes each. Each segment in main memory is 512 bytes in size.

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0--n.

Segments A to D are also called information memory.

Segment A contains calibration data. After reset segment A is protected against programming and erasing.

It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data

is required.

MSP430F2012IPWR Datasheet(PDF) 15 Page - Texas Instruments

MSP430F2012IPWR Datasheet(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL