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LT3437

3437fc

SHUTDOWN FUNCTION AND UNDERVOLTAGE

LOCKOUT

The SHDN pin on the LT3437 controls the operation of the

IC. When the voltage on the SHDN pin is below the 1.3V

shutdown threshold, the LT3437 is placed in a “zero”

supply current state. Driving the SHDN pin above the

shutdown threshold enables normal operation. The SHDN

pin has an internal sink current with a typical value of 5

µA.

In addition to the shutdown feature, the LT3437 has an

undervoltage lockout function. When the input voltage is

below 2.5V, switching will be disabled. The undervoltage

lockout threshold doesn’t have any hysteresis and is

mainly used to insure that all internal voltages are at the

correct level before switching is enabled. If an undervolt-

age lockout function with hysteresis is needed to limit

input current at low VIN to VOUT ratios, refer to Figure 7 and

the following:

UVLO

SHDN

HYST

OUT

⎛

⎝⎜

⎞

⎠⎟

()

R1 should be chosen to minimize quiescent current during

normal operation by the following equation:

SHDN TYP

= ()()

–

()

Example:

12 2

15 5

51 3

649

408

()

Ω

()

ΩΩ

Ω

–

––

(Nearest 1% 6.49M )

R2 =

1.3

7 – 1.3

1.3M

(Nearest 1% 412k)

See the Typical Performance Characteristics section for

graphs of SHDN and VIN currents verses input voltage.

Figure 7. Undervoltage Lockout

SYNCHRONIZING

Oscillator synchronization to an external input is achieved

by connecting a TTL logic-compatible square wave with a

duty cycle between 25% and 75% to the LT3437 SYNC

pin. The synchronizing range is equal to initial operating

frequency up to 700kHz. This means that minimum

practical sync frequency is equal to the worst-case high

self-oscillating frequency (240kHz), not the typical oper-

ating frequency of 200kHz. Caution should be used when

synchronizing above 300kHz, because at higher sync

frequencies the amplitude of the internal slope compen-

sation used to prevent subharmonic switching is re-

duced. This type of subharmonic switching only occurs at

input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See

Frequency Compensation section for a discussion of an

entirely different cause of subharmonic switching before

assuming that the cause is insufficient slope compensa-

tion. Application Note 19 has more details on the theory

of slope compensation.

If the FB pin voltage is below 0.9V (power-up or output

short-circuit conditions), the sync function is disabled.

This allows the frequency foldback to operate to avoid

hazardous conditions for the SW pin.

If a synchronization signal or logic-level above 2V is

present at the SYNC pin, Burst Mode operation is disabled.

Burst Mode operation can be enabled or disabled on the

fly. If no synchronization or Burst Mode defeat is required,

this pin should be connected to ground.

APPLICATIO S I FOR ATIO

ENABLE

1.3V

3437 F07

µA

SHDN

2.5V

–

SHDN

COMP

–

VIN

COMP

VIN

VOUT

LT3437

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