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LT3437IDD Datasheet(PDF) 20 Page - Linear Technology |
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LT3437IDD Datasheet(HTML) 20 Page - Linear Technology |
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20 / 28 page ![]() 20 LT3437 3437fc LAYOUT CONSIDERATIONS As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum efficiency, switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted, the high speed switching current path, shown in Figure 8, must be kept as short as possible. This is implemented in the suggested layouts of Figure 9. Shortening this path will also reduce the parasitic trace inductance of approximately 25nH/inch. At switch off, this parasitic inductance produces a flyback spike across the LT3437 switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the LT3437 that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. The VC and FB components should be kept as far away as possible from the switch and boost nodes. The LT3437 pinout has been designed to aid in this. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic oscillation. Board layout also has a significant effect on thermal resistance. Pin 4/Pin 8 and the exposed die pad, Pin 11/Pin 17, are connected by a continuous copper plate that runs under the LT3437 die. This is the best thermal path for heat out of the package. Reducing the thermal resistance from Pin 4 and the exposed pad onto the board will reduce die temperature and increase the power capability of the LT3437. This is achieved by providing as much copper area as possible around the exposed pad. Adding multiple solder filled feedthroughs, under and around this pad, to an internal ground plane will also help. Similar treatment to the catch diode and coil terminations will reduce any additional heating effects. Figure 8. High Speed Switching Path C2 C1 3437 F08 D1 L1 VIN LT3437 VOUT VIN SW HIGH FREQUENCY CIRCULATION PATH + LOAD APPLICATIO S I FOR ATIO |
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