Figure 1: Logic Symbol

Device Requirements

MC-ACT-UL2LINK (UTOPIA Level 2 LINK Interface)

Device

Speed

Ingress / Egress

C cells

R cells

Tiles

RAM's

A3P250

88 / 88 MHz

-

-

1833 (30%)

4

APA075

77 / 62 MHz

-

-

2163 (70%)

8

AX125

108 / 98 MHz

812 (60%)

640 (95%)

-

4

Table 1: Device Utilization and Performance*

*Note: These numbers obtained with 1 channel and 16-bit data size.

Verification and Compliance

The testbench is self-checking, which means that if there is an error detected in the start word, end word, or payload the testbench will assert one or both of two error

signals. This core has also been used successfully in customer designs.

MDS8076

rd_data

rd_enb

rd_clk

flag

decrement

wr_data

wr_enb

wr_clk

a_full

increment

egr_data

egr_addr

egr_soc

egr_enb_n

egr_clav

egr_prty

egr_clk

ing_perr

TX FIFO

TX Master

RX Master

RX FIFO

ing_data

ing_addr

ing_soc

ing_enb_n

ing_clav

ing_prty

ing_clk