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LTC1272

1272fb

APPLICATI

I FOR ATIO

the foil width for these tracks should be as wide as

possible.

Noise: Input signal leads to AIN and signal return leads

from AGND (pin 3) should be kept as short as possible to

minimize input noise coupling. In applications where this

is not possible, a shielded cable between source and ADC

is recommended. Also, since any potential difference in

grounds between the signal source and ADC appears as an

error voltage in series with the input signal, attention

should be paid to reducing the ground circuit impedances

as much as possible.

In applications where the LTC1272 data outputs and

control signals are connected to a continuously active

microprocessor bus, it is possible to get LSB errors in

conversion results. These errors are due to feedthrough

from the microprocessor to the successive approximation

comparator. The problem can be eliminated by forcing the

microprocessor into a Wait state during conversion (see

Slow Memory Mode interfacing), or by using three-state

buffers to isolate the LTC1272 data bus.

Timing and Control

Conversion start and data read operations are controlled

by three LTC1272 digital inputs; HBEN, CS and RD. Figure

12 shows the logic structure associated with these inputs.

The three signals are internally gated so that a logic “0” is

required on all three inputs to initiate a conversion. Once

initiated it cannot be restarted until conversion is com-

plete. Converter status is indicated by the BUSY output,

and this is low while conversion is in progress.

LTC1272 • TA13

AIN

AGND

VREF

VDD DGND

LTC1272

DIGITAL

SYSTEM

–

ANALOG GROUND PLANE

GROUND CONNECTION

TO DIGITAL CIRCUITRY

ANALOG

INPUT

CIRCUITRY

Figure 11. Power Supply Grounding Practice

Application Hints

Wire wrap boards are not recommended for high resolu-

tion or high speed A/D converters. To obtain the best

performance from the LTC1272 a printed circuit board is

required. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track or

underneath the LTC1272. The analog input should be

screened by AGND.

A single point analog ground separate from the logic

system ground should be established with an analog

ground plane at pin 3 (AGND) or as close as possible to the

LTC1272, as shown in Figure 11. Pin 12 (LTC1272 DGND)

and all other analog grounds should be connected to this

single analog ground point. No other digital grounds

should be connected to this analog ground point. Low

impedance analog and digital power supply common

returns are essential to low noise operation of the ADC and

Ω

LTC1272 • TA12

–

AIN

AGND

20k

200

Ω

VIN

0V TO 5V

ANALOG

INPUT

LT1007

*ADDITIONAL PINS OMITTED FOR CLARITY

LTC1272

Figure 10. Unipolar 0V to 5V Operation with Gain Error Adjust

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