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LTC4444 Datasheet(PDF) 7 Page - Linear Technology |
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LTC4444 Datasheet(HTML) 7 Page - Linear Technology |
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7 / 12 page ![]() LTC4444 7 4444f BLOCK DIAGRAM 3 6 7 9 HIGH SIDE LEVEL SHIFTER VCC UVLO LDO VINT VCC GND 7.2V TO 13.5V BOOST VIN UP TO 100V TG 8 TS BG 4444 BD 1 TINP BINP 2 5 NC LOW SIDE LEVEL SHIFTER ANTISHOOT-THROUGH PROTECTION VCC VCC 4 TIMING DIAGRAM 90% INPUT RISE/FALL TIME < 10ns TINP (BINP) BG (TG) BINP (TINP) TG (BG) 90% 90% tr tf tPHL tPLH 10% 4444 TD 10% 10% OPERATION Overview The LTC4444 receives ground-referenced, low voltage digital input signals to drive two N-channel power MOSFETs in a synchronous buck power supply configuration. The gate of the low side MOSFET is driven either to VCC or GND, depending on the state of the input. Similarly, the gate of the high side MOSFET is driven to either BOOST or TS by a supply bootstrapped off of the switching node (TS). Input Stage The LTC4444 employs CMOS compatible input thresholds that allow a low voltage digital signal to drive standard power MOSFETs. The LTC4444 contains an internal voltage regulator that biases both input buffers for high side and low side inputs, allowing the input thresholds (VIH = 2.75V, VIL = 2.3V) to be independent of variations in VCC. The 450mV hysteresis between VIH and VIL eliminates false triggering due to noise during switching transitions. However, care should be taken to keep both input pins (TINP and BINP) from any noise pickup, especially in high frequency, high voltage applications. The LTC4444 input buffers have high input impedance and draw negligible input current, simplifying the drive circuitry required for the inputs. |
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