LTC2272 datasheet(6/44 Pages) LINER

6 / 44 page

LTC2273/LTC2272

22732f

TIMING CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 4)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND (unless otherwise

noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: VDD = 3.3V, fSAMPLE = 105MHz differential ENC+/ENC– = 2VP-P sine

wave with 1.6V common mode, input range = 2.25VP-P with differential

drive (PGA = 0), unless otherwise speciﬁed.

Note 5: Integral nonlinearity is deﬁned as the deviation of a code from

a “best ﬁt straight line” to the transfer curve. The deviation is measured

from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –1/2LSB when the

output code ﬂickers between 0000 0000 0000 0000 and 1111 1111 1111

1111 in 2’s complement output mode.

Note 7: Guaranteed by design, not subject to test.

Note 8: VDD = 3.3V, fSAMPLE = 80Msps (LTC2273) or 65Msps (LTC2272)

input range = 2.25VP-P with differential drive.

Note 9: Recommended operating conditions.

Note 10: The dynamic current of the switched capacitors analog inputs

can be large compared to the leakage current and will vary with the sample

rate.

Note 11: Leakage current will have higher transient current at power up.

Keep drive resistance at or below 1k.

The

l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. AIN = –1dBFS. (Note 4)

POWER REQUIREMENTS

SYMBOL PARAMETER

CONDITIONS

LTC2273

LTC2272

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

VDD

Analog Supply Voltage

l 3.135

3.3

3.465

3.135

3.3

3.465

PSHDN

Shutdown Power

SHDN = VDD

OVDD

Output Supply Voltage

CMLOUT Directly-Coupled, 50Ω to OVDD (Note 7)

CMLOUT Directly-Coupled, 100Ω Diff. (Note 7)

CMLOUT AC-Coupled (Note 7)

1.2

1.4

VDD

1.2

1.4

VDD

IVDD

Analog Supply Current

DC Input

233

370

300

340

IOVDD

Output Supply Current

CMLOUT Directly-Coupled, 50Ω to OVDD

CMLOUT Directly-Coupled, 100Ω Diff.

CMLOUT AC-Coupled

PDIS

Power Dissipation

DC Input

1100

1221

990

1122

SYMBOL PARAMETER

CONDITIONS

LTC2273

LTC2272

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

Sampling Frequency

(Note 9)

MHz

tCONV

Conversion Period

1/fS

ENC Clock Low Time

(Note 7)

4.06

6.25

5.03

7.69

ENC Clock High Time

(Note 7)

4.06

6.25

5.03

7.69

tAP

Sample-and-Hold Aperture Delay

0.7

tBIT, UI

Period of a Serial Bit

tCONV/20

tJIT

Total Jitter of CMLOUT± (P-P)

BER = 1E–12 (Note 7)

0.35

tR, tF

Differential Rise and Fall Time of

CMLOUT± (20% to 80%)

RTERM = 50Ω, CL = 2pF

(Note 7)

110

tSU

SYNC to ENC Clock Setup Time

(Note 7)

tHD

ENC Clock to SYNC Hold Time

(Note 7)

2.5

tCS

ENC Clock to SYNC Delay

(Note 7)

tHD

tCONV – tSU

tHD

tCONV – tSU

LATP

Pipeline Latency

Cycles

LATSC

Latency from SYNC Active to COMMA Out

Cycles

LATSD

Latency from SYNC Release to DATA Out

Cycles

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