LTC2485CDD datasheet(5/40 Pages) LINER

5 / 40 page

LTC2485

2485fa

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fEOSC

External Oscillator Frequency Range

●

4000

kHz

tHEO

External Oscillator High Period

●

0.125

100

µs

tLEO

External Oscillator Low Period

●

0.125

100

µs

tCONV_1

Conversion Time for 1x Speed Mode

50Hz Mode

●

157.2

160.3

163.5

60Hz Mode

●

131.0

133.6

136.3

Simultaneous 50Hz/60Hz Mode

●

144.1

146.9

149.9

External Oscillator (Note 10)

●

41036/fEOSC

tCONV_2

Conversion Time for 2x Speed Mode

50Hz Mode

●

78.7

80.3

81.9

60Hz Mode

●

65.6

66.9

68.2

Simultaneous 50Hz/60Hz Mode

●

72.2

73.6

75.1

External Oscillator (Note 10)

●

20556/fEOSC

The

● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 3)

TI I G CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: VCC = 2.7V to 5.5V unless otherwise specified.

VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2, FS = 0.5VREF;

VIN = IN

+ – IN–, VINCM = (IN+ + IN–)/2.

Note 4: Use internal conversion clock or external conversion clock source

with fEOSC = 307.2kHz unless otherwise specified.

Note 5: Guaranteed by design, not subject to test.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external

oscillator).

Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external

oscillator).

Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =

280kHz

±2% (external oscillator).

Note 10: The external oscillator is connected to the CA0/F0 pin. The

external oscillator frequency, fEOSC, is expressed in kHz.

Note 11: The converter uses the internal oscillator.

Note 12: The output noise includes the contribution of the internal

calibration operations.

Note 13: Guaranteed by design and test correlation.

Note 14: CB = capacitance of one bus line in pF.

Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.

The

● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 15)

I2C TI I G CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSCL

SCL Clock Frequency

●

400

kHz

tHD(SDA)

Hold Time (Repeated) START Condition

●

0.6

µs

tLOW

LOW Period of the SCL Clock Pin

●

1.3

µs

tHIGH

HIGH Period of the SCL Clock Pin

●

0.6

µs

tSU(STA)

Set-Up Time for a Repeated START Condition

●

0.6

µs

tHD(DAT)

Data Hold Time

●

0.9

µs

tSU(DAT)

Data Set-Up Time

●

100

Rise Time for Both SDA and SCL Signals

(Note 14)

●

20+0.1CB

300

Fall Time for Both SDA and SCL Signals

(Note 14)

●

20+0.1CB

300

tSU(STO)

Set-Up Time for STOP Condition

●

0.6

µs

LTC2485CDD Datasheet(PDF) 5 Page - Linear Technology

LTC2485CDD Datasheet(HTML) 5 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL