BQ3285ECSSTR datasheet(4/26 Pages) TI

4 / 26 page

Functional Description

Address Map

The bq3285EC/LC provides 14 bytes of clock and con-

trol/status registers and 242 bytes of general nonvolatile

storage.

Figure 1 illustrates the address map for the

bq3285EC/LC.

Update Period

The update period for the bq3285EC/LC is one second.

The bq3285EC/LC updates the contents of the clock and

calendar locations during the update cycle at the end of

each update period (see Figure 2). The alarm flag bit

may also be set during the update cycle.

The bq3285EC/LC copies the local register updates into

the user buffer accessed by the host processor. When a 1

is written to the update transfer inhibit bit (UTI) in reg-

ister B, the user copy of the clock and calendar bytes re-

mains unchanged, while the local copy of the same bytes

continues to be updated every second.

The update-in-progress bit (UIP) in register A is set

tBUC time before the beginning of an update cycle (see

Figure 2). This bit is cleared and the update-complete

flag (UF) is set at the end of the update cycle.

Figure 1. Address Map

Figure 2. Update Period Timing and UIP

bq3285EC/LC

July 1996

BQ3285ECSSTR Datasheet(PDF) 4 Page - Texas Instruments