EPF6016 datasheet(21/52 Pages) ALTERA

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Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet

Table 5 summarizes the FastTrack Interconnect resources available in

each FLEX 6000 device.

In addition to general-purpose I/O pins, FLEX 6000 devices have four

dedicated input pins that provide low-skew signal distribution across the

device. These four inputs can be used for global clock and asynchronous

clear control signals. These signals are available as control signals for all

LEs in the device. The dedicated inputs can also be used as general-

purpose data inputs because they can feed the local interconnect of each

LAB in the device. Using dedicated inputs to route data signals provides

a fast path for high fan-out signals.

The local interconnect from LABs located at either end of two rows can

drive a global control signal. For instance, in an EPF6016 device, LABs C1,

D1, C22, and D22 can all drive global control signals. When an LE drives

a global control signal, the dedicated input pin that drives that signal

cannot be used. Any LE in the device can drive a global control signal by

driving the FastTrack Interconnect into the appropriate LAB. To minimize

delay, however, the Altera software places the driving LE in the

appropriate LAB. The LE-driving-global signal feature is optimized for

speed for control signals; regular data signals are better routed on the

FastTrack Interconnect and do not receive any advantage from being

routed on global signals. This LE-driving-global control signal feature is

controlled by the designer and is not used automatically by the Altera

software. See Figure 11.

Table 5. FLEX 6000 FastTrack Interconnect Resources

Device

Rows

Channels per

Row

Columns

Channels per

Column

EPF6010A

144

EPF6016

EPF6016A

144

EPF6024A

186

EPF6016 Datasheet(PDF) 21 Page - Altera Corporation