EP2S15 datasheet(91/238 Pages) ALTERA

91 / 238 page

Altera Corporation

2–83

May 2007

Stratix II Device Handbook, Volume 1

Stratix II Architecture

Figure 2–56. DQS Phase-Shift Circuitry

Notes (1), (2), (3), (4)

Notes to Figure 2–56:

(1)

There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device. There are

up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.

(2)

The

Δt module represents the DQS logic block.

(3)

Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed

the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the phase-

shift circuitry.

(4)

You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS

phase-shift circuitry on the bottom of the device.

These dedicated circuits combined with enhanced PLL clocking and

phase-shift ability provide a complete hardware solution for interfacing

to high-speed memory.

For more information on external memory interfaces, refer to the

External Memory Interfaces in Stratix II & Stratix II GX Devices chapter in

volume 2 of the Stratix II Device Handbook or the Stratix II GX Device

Handbook.

Programmable Drive Strength

The output buffer for each Stratix II device I/O pin has a programmable

drive strength control for certain I/O standards. The LVTTL, LVCMOS,

SSTL, and HSTL standards have several levels of drive strength that the

user can control. The default setting used in the Quartus II software is the

maximum current strength setting that is used to achieve maximum I/O

performance. For all I/O standards, the minimum setting is the lowest

drive strength that guarantees the IOH/IOL of the standard. Using

minimum settings provides signal slew rate control to reduce system

noise and signal overshoot.

DQS

DQSn

DQS

DQSn

DQS

DQSn

From PLL 5 (3)

CLK[15..12]p (2)

to IOE

Δt

to IOE

DQS

Phase-Shift

Circuitry

Δt

DQS Logic

Blocks

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