EP2S15 datasheet(11/238 Pages) ALTERA

11 / 238 page

Altera Corporation

2–3

May 2007

Stratix II Device Handbook, Volume 1

Stratix II Architecture

The number of M512 RAM, M4K RAM, and DSP blocks varies by device

along with row and column numbers and M-RAM blocks. Table 2–1 lists

the resources available in Stratix II devices.

Logic Array

Blocks

Each LAB consists of eight ALMs, carry chains, shared arithmetic chains,

LAB control signals, local interconnect, and register chain connection

lines. The local interconnect transfers signals between ALMs in the same

LAB. Register chain connections transfer the output of an ALM register to

the adjacent ALM register in an LAB. The Quartus® II Compiler places

associated logic in an LAB or adjacent LABs, allowing the use of local,

shared arithmetic chain, and register chain connections for performance

and area efficiency. Figure 2–2 shows the Stratix II LAB structure.

Table 2–1. Stratix II Device Resources

Device

M512 RAM

Columns/Blocks

M4K RAM

Columns/Blocks

M-RAM

Blocks

DSP Block

Columns/Blocks

LAB

Columns

LAB Rows

EP2S15

4 / 104

3 / 78

2 / 12

EP2S30

6 / 202

4 / 144

2 / 16

EP2S60

7 / 329

5 / 255

3 / 36

EP2S90

8 / 488

6 / 408

3 / 48

EP2S130

9 / 699

7 / 609

3 / 63

EP2S180

11 / 930

8 / 768

4 / 96

100

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