SN74ACT3631

512

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

7

POST OFFICE BOX 655303

serial load

To serially program the X and Y registers, the device is reset with FS0/SD and FS1/SEN high during the

low-to-high transition of RST. After this reset is complete, the X- and Y-register values are loaded bitwise through

FS0/SD on each low-to-high transition of CLKA that FS1/SEN is low. Writes of 18 bits are needed to complete

the programming. The first bit write stores the most-significant bit of the Y register, and the last bit write stores

the least-significant bit of the X register. Each register value can be programmed from 1 to 508.

When the option to program the offset registers serially is chosen, the input-ready (IR) flag remains low until

all register bits are written. The IR flag is set high by the low-to-high transition of CLKA after the last bit is loaded

to allow normal FIFO operation.

FIFO write/read operation

The state of the port-A data (A0 – A35) outputs is controlled by the port-A chip select (CSA) and the port-A

write/read select (W/RA). The A0 – A35 outputs are in the high-impedance state when either CSA or W/RA is

high. The A0 – A35 outputs are active when both CSA and W/RA are low.

Data is loaded into the FIFO from the A0 – A35 inputs on a low-to-high transition of CLKA when CSA and the

port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the input-ready (IR) flag are high

(see Table 2). Writes to the FIFO are independent of any concurrent FIFO reads.

Table 2. Port-A Enable Function Table

CSA

W/RA

ENA

MBA

CLKA

A0 – A35 OUTPUTS

PORT FUNCTION

H

X

X

X

X

In high-impedance state

None

L

H

L

X

X

In high-impedance state

None

L

H

H

L

↑

In high-impedance state

FIFO write

L

H

H

H

↑

In high-impedance state

Mail1 write

L

L

L

L

X

Active, mail2 register

None

L

L

H

L

↑

Active, mail2 register

None

L

L

L

H

X

Active, mail2 register

None

L

L

H

H

↑

Active, mail2 register

Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A, with the exception that the port-B write/read select

(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0 – B35) outputs is

controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0 – B35 outputs are

in the high-impedance state when either CSB is high or W/RB is low. The B0 – B35 outputs are active when CSB

is low and W/RB is high.

Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and the port-B

mailbox select (MBB) are low, W/RB, the port-B enable (ENB), and the output-ready (OR) flag are high

(see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.