SN74ALVC7813

64

× 18

LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS594A – OCTOBER 1997 – REVISED APRIL 1998

10

POST OFFICE BOX 655303

timing requirements over recommended operating conditions (see Figures 1 through 5)

’ALVC7813-20

’ALVC7813-25

’ALVC7813-40

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

50

40

25

MHz

D0–D17 high or low

9

10

14

WRTCLK high or low

7

8

12

RDCLK high or low

7

8

12

tw

Pulse duration

PEN low

9

9

12

ns

WRTEN1 high, WRTEN2 low

8

8

12

OE1, OE2 low

9

9

12

RDEN low

8

8

12

D0–D17 before WRTCLK

↑

5

5

5

WRTEN1, WRTEN2 before WRTCLK

↑

5

5

5

OE1, OE2 before RDCLK

↑

5

6

6

tsu

Setup time

RDEN before RDCLK

↑

5

5

7

ns

Reset: RESET low before first WRTCLK

↑

and RDCLK

↑†

6

6

6

PEN before WRTCLK

↑

6

6

6

D0–D17 after WRTCLK

↑

0

0

0

WRTEN1, WRTEN2 after WRTCLK

↑

0

0

0

th

Hold time

OE1, OE2, RDEN after RDCLK

↑

0

0

0

ns

th

Hold time

Reset: RESET low after fourth WRTCLK

↑

and RDCLK

↑†

2

2

2

ns

PEN low after WRTCLK

↑

2

2

2

† To permit the clock pulse to be utilized for reset purposes

switching characteristics over recommended ranges of supply voltage and operating free-air

PARAMETER

FROM

TO

’ALVC7813-20

’ALVC7813-25

’ALVC7813-40

UNIT

PARAMETER

(OUTPUT)

(INPUT)

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

fmax

WRTCLK or RDCLK

50

40

25

MHz

RDCLK

↑

Any Q

4

13

4

15

4

20

WRTCLK

↑

IR

3

11

3

13

3

15

tpd

RDCLK

↑

OR

3

11

3

13

3

15

ns

WRTCLK

↑

AF/AE

7

19

7

21

7

23

RDCLK

↑

AF/AE

7

19

7

21

7

23

tPLH

WRTCLK

↑

HF

7

17

7

19

7

21

ns

tPHL

RDCLK

↑

HF

7

18

7

20

7

22

ns

tPLH

RESET low

AF/AE

2

11

2

13

2

15

ns

tPHL

RESET low

HF

2

12

2

14

2

16

ns

ten

OE1, OE2

Any Q

2

11

2

11

2

14

ns

tdis

OE1, OE2

Any Q

2

11

2

14

2

14

ns

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

Outputs enabled

CL = 50 pF,

f = 5 MHz

53

pF