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FT4232H Datasheet(PDF) 19 Page - Future Technology Devices International Ltd. |
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FT4232H Datasheet(HTML) 19 Page - Future Technology Devices International Ltd. |
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19 / 43 page ![]() Copyright © 2009 Future Technology Devices International Limited 19 Document No.: FT_000060 FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC Datasheet Version 2.05 Clearance No.: FTDI#78 4.3.3 RS485 Configuration Figure 4.3 illustrates how the FT4232H can be configured as a dual RS485 interface. The FT4232H can have all 4 channels connected as RS485, but only channel A and channel C are shown for clarity. Figure 4.3 Dual RS485 Configuration In this case both channel A and channel C are configured as RS485 operating at TTL levels. This example uses two Sipex SP491 devices but there are similar parts available from Maxim and Analog Devices amongst others. The SP491 is a RS485 device in a compact 8 pin SOP package. It has separate enables on both the transmitter and receiver. With RS485, the transmitter is only enabled when a character is being transmitted from the UART. The TXDEN pins on the FT4232H are provided for exactly that purpose, and so the transmitter enables are wired to the TXDEN’s. The receiver enable is active low, so it is wired to the PWREN# pin to disable the receiver when in USB suspend mode. RS485 is a multi-drop network – i.e. many devices can communicate with each other over a single two wire cable connection. The RS485 cable requires to be terminated at each end of the cable. Links are provided to allow the cable to be terminated if the device is physically positioned at either end of the cable. In this example the data transmitted by the FT4232H is also received by the device that is transmitting. This is a common feature of RS485 and requires the application software to remove the transmitted data from the received data stream. With the FT4232H it is possible to do this entirely in hardware – simply modify the schematic so that RXD of the FT4232H is the logical OR of the SP481 receiver output with TXDEN using an HC32 or similar logic gate. D B 9 - M R S 4 8 5 C h a n n e l A D M _ A G N D 1 2 0 R D P A V C C 4 3 6 2 1 7 8 5 D R S P 4 8 1 L I N K F T 4 2 3 2 H T X D R X D R T S # C T S # D T R # D S R # D C D # T X D E N 1 6 1 7 1 8 1 9 2 1 2 2 2 3 2 4 P W R E N # 6 0 3 8 3 9 4 0 4 1 4 3 4 4 4 5 4 6 D B 9 - M R S 4 8 5 C h a n n e l C D M _ B G N D 1 2 0 R D P _ B V C C 4 3 6 2 1 7 8 5 D R S P 4 8 1 L I N K T X D R X D R T S # C T S # D T R # D S R # D C D # T X D E N |
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