TMS320VC549 datasheet(41/60 Pages) TI

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TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial port receive timing

timing requirements over recommended operating conditions for serial port receive [H = 0.5 tc(CO)]

(see Figure 21)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

tc(SCK)

Cycle time, serial port clock

†

tf(SCK)

Fall time, serial port clock

tr(SCK)

Rise time, serial port clock

tw(SCK)

Pulse duration, serial port clock low/high

tsu(FSR)

Setup time, FSR before CLKR falling edge

th(FSR)

Hold time, FSR after CLKR falling edge

th(DR)

Hold time, DR after CLKR falling edge

tsu(DR)

Setup time, DR before CLKR falling edge

† The serial port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

BIT

FSR

CLKR

8/16

7/15

tsu(DR)

tsu(FSR)

th(FSR)

tw(SCK)

tr(SCK)

tf(SCK)

tw(SCK)

th(DR)

tc(SCK)

Figure 21. Serial Port Receive Timing

TMS320VC549 Datasheet(PDF) 41 Page - Texas Instruments

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