May 2008

ASM3P623S00B/E

rev 0.5

Timing-Safe™ Peak EMI Reduction IC

6 of 15

Notice: The information in this document is subject to change without notice.

Switching Characteristics

Parameter

Test Conditions

Min

Typ

Max

Unit

Input Frequency

4

20

MHz

Output Frequency

30pF load

4

20

MHz

Duty Cycle

Measured at VDD/2

40

50

60

%

Output Rise Time

7, 8

Measured between 0.8V and 2.0V

2.5

nS

Output Fall Time

7, 8

Measured between 2.0V and 0.8V

2.5

nS

Output-to-output skew

7, 8

All outputs equally loaded with SSOFF

250

pS

Delay, CLKIN Rising Edge to

CLKOUT Rising Edge

8

Measured at VDD /2 with SSOFF

±350

pS

Device-to-Device Skew

8

Measured at VDD/2 on the CLKOUT pins

of the device

700

pS

Cycle-to-Cycle Jitter

7, 8

Loaded outputs

±250

pS

PLL Lock Time

8

Stable power supply, valid clock presented

on CLKIN pin

1.0

mS

Note: 7. All parameters specified with 30pF loaded outputs.

8. Parameter is guaranteed by design and characterization. Not 100% tested in production

Switching Waveforms

Duty Cycle Timing

All Outputs Rise/Fall Time

OUTPUT

OUTPUT

0V

3.3V

0.8V

2V

0.8V

2V